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1996 data sheet mos integrated circuit description the MC-428LFC72 is a 8,388,608 words by 72 bits dynamic ram module on which 9 pieces of 64 m dram: m pd4265805 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed cicuit board. decoupling capacitors are mounted on power supply line for noise reduction. features ? buffered type ? edo (hyper page mode) ? 8,388,608 words by 72 bits organization ? fast access and cycle time family access time r/w cycle time edo (hyper page mode) power consumption (max.) (max.) (min.) cycle time (min.) active standby MC-428LFC72-a50 50 ns 84 ns 20 ns 4.60 w 246.6 mw MC-428LFC72-a60 60 ns 104 ns 25 ns 3.96 w (cmos level input) ? 4,096 refresh cycles/64 ms ? /cas before /ras refresh, /ras only refresh, hidden refresh ? 168-pin dual in-line memory module (pin pitch = 1.27 mm) ? single +3.3 v 0.3 v power supply ordering information part number access time package mounted devices (max.) MC-428LFC72fh-a50 50 ns 168-pin dual in-line memory module 9 pieces of m pd4265805g5 (socket type) (400 mil tsop (ii)) MC-428LFC72fh-a60 60 ns edge connector: gold plated [double side] MC-428LFC72fb-a50 50 ns 9 pieces of m pd4265805le (400 mil soj) MC-428LFC72fb-a60 60 ns [double side] MC-428LFC72 3.3v operation 8m-word by 72-bit dynamic ram module buffered type, edo the cinformation in this document is subject to change without notice. document no. m11916ej3v0ds00 (3rd edition) date published april 1997 n printed in japan the mark shows major revised points.
MC-428LFC72 2 pin configuration 168-pin dual in-line memory module socket type (edge connector: gold plated) [MC-428LFC72fh, 428lfc72fb] /xxx indicates active low signal. pd and id table pin pin access time name no. 50 ns 60 ns pd1 79 h h pd2 163 l l pd3 80 h h pd4 164 h h pd5 81 h h pd6 165 l h pd7 82 l h pd8 166 l l id0 83 gnd gnd id1 167 gnd gnd remark h: v oh , l: v ol a0 - a11, b0 : address inputs [ row: a0 - a11, b0, column: a0 - a10, b0 ] i/o0 - i/o71 : data inputs/outputs /ras0, /ras2 : row address strobe /cas0, /cas4 : column address strobe /we0, /we2 : write enable /oe0, /oe2 : output enable /pde : presence detect enable pd1 - pd8 : presence detect pins id0, id1 : identity pins v cc : power supply gnd : ground nc : no connection gnd i/o 36 i/o 37 i/o 38 i/o 39 v cc i/o 40 i/o 41 i/o 42 i/o 43 85 86 87 88 89 90 91 92 93 94 i/o 44 gnd i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 v cc i/o 50 i/o 51 i/o 52 i/o 53 gnd nc nc v cc nc nc nc nc nc gnd a1 a3 a5 a7 a9 a11 nc v cc 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 nc b0 gnd nc nc nc nc /pde v cc nc nc i/o 54 i/o 55 gnd i/o 56 i/o 57 i/o 58 i/o 59 v cc i/o 60 nc nc nc nc i/o 61 i/o 62 i/o 63 gnd i/o 64 i/o 65 i/o 66 i/o 67 v cc i/o 68 i/o 69 i/o 70 i/o 71 gnd pd2 pd4 pd6 pd8 id1 v cc 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 gnd i/o 0 i/o 1 i/o 2 i/o 3 v cc i/o 4 i/o 5 i/o 6 i/o 7 1 2 3 4 5 6 7 8 9 10 i/o 8 gnd i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 v cc i/o 14 i/o 15 i/o 16 i/o 17 gnd nc nc v cc /we0 /cas0 nc /ras0 /oe0 gnd a0 a2 a4 a6 a8 a10 nc v cc 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc nc gnd /oe2 /ras2 /cas4 nc /we2 v cc nc nc i/o 18 i/o 19 gnd i/o 20 i/o 21 i/o 22 i/o 23 v cc i/o 24 nc nc nc nc i/o 25 i/o 26 i/o 27 gnd i/o 28 i/o 29 i/o 30 i/o 31 v cc i/o 32 i/o 33 i/o 34 i/o 35 gnd pd1 pd3 pd5 pd7 id0 v cc 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
MC-428LFC72 3 block diagram a0 b0 a1 - a11 a0 : d0 - d4 a0 : d5 - d8 d0 - d8 d0 /ras0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 /oe0 /we0 /cas0 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 /ras /we /oe /cas i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 d1 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 d2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 d3 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 d4 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 d5 /ras2 /oe2 /we2 /cas4 d6 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 d7 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 d8 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 60 i/o 71 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 v cc or gnd nc or gnd d0 - d8 d0 - d8 c0 - c8 /pde pd1 - pd8 id0, id1 v cc gnd /ras /we /oe /cas i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 /ras /we /oe /cas i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 /ras /we /oe /cas i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 /ras /we /oe /cas i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 /ras /we /oe /cas i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 /ras /we /oe /cas i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 /ras /we /oe /cas /ras /we /oe /cas remark d0 - d8: m pd4265805 (8m words by 8 bits organization)
MC-428LFC72 4 electrical specifications ? all voltages are referenced to gnd. ? after power up (v cc 3 v cc (min.) ), wait more than 100 m s (/ras, /cas inactive) and then, execute eight /cas before /ras or /ras only refresh cycles as dummy cycles to initialize internal circuit. absolute maximum ratings parameter symbol condition rating unit voltage on any pin relative to gnd v t C0.5 to +4.6 v supply voltage v cc C0.5 to +4.6 v output current i o 50 ma power dissipation p d 9w operating ambient temperature t a 0 to +70 ?c storage temperature t stg C55 to +125 ?c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 +0.8 v operating ambient temperature t a 070?c capacitance (t a = 25 ?c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, b0 20 pf c i2 /we0, /we2 20 c i3 /ras0, /ras2 60 c i4 /cas0, /cas4 20 c i5 /oe0, /oe2 20 data input/output capacitance c i/o i/o0 - i/o71 30 pf
MC-428LFC72 5 dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes operating current i cc1 /ras, /cas cycling t rac = 50 ns 1,279 ma 1, 2, 3 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 1,099 standby current i cc2 /ras, /cas 3 v ih (min.) , i o = 0 ma 73.0 ma /ras, /cas 3 v cc C 0.2 v, i o = 0 ma 68.5 /ras only refresh current i cc3 /ras cycling, /cas 3 v ih (min.) t rac = 50 ns 1,279 ma 1, 2, 3 ,4 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 1,099 operating current i cc4 /ras v il (max.) , /cas cycling t rac = 50 ns 1,009 ma 1, 2, 5 (hyper page mode (edo)) t hpc = t hpc (min.) , i o = 0 ma t rac = 60 ns 919 /cas before /ras i cc5 /ras cycling t rac = 50 ns 1,279 ma 1, 2 refresh current t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 1,099 input leakage current i i (l) v i = 0 to 3.6 v /ras C45 +45 m a all other pins not under test = 0 v others C5 +5 output leakage current i o (l) v o = 0 to 3.6 v C5 +5 m a output is disabled (hi-z) high level output voltage v oh i o = C2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v notes 1. i cc1 , i cc3 , i cc4 and i cc5 depend on cycle rates (t rc and t hpc ). 2. specified values are obtained with outputs unloaded. 3. i cc1 and i cc3 are measured assuming that address can be changed once or less during /ras v il (max.) and /cas 3 v ih (min.) . 4. i cc3 is measured assuming that all column address inputs are held at either high or low. 5. i cc4 is measured assuming that all column address inputs are switched only once during each hyper page (edo) cycle.
MC-428LFC72 6 v ih (min.) = 2.0 v v il (max.) = 0.8 v v oh (min.) = 2.0 v v ol (max.) = 0.8 v t t = 2 ns t t = 2 ns ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions (1) input timing specification (2) output timing specification (3) output load condition v cc 1,180 w 870 w 100 pf i/o c l common to read, write, read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t rc 84 C 104 C ns /ras precharge time t rp 30 C 40 C ns /cas precharge time t cpn 7C10Cns /ras pulse width t ras 50 10,000 60 10,000 ns /cas pulse width t cas 8 10,000 10 10,000 ns /ras hold time t rsh 18 C 20 C ns /cas hold time t csh 33 C 35 C ns /ras to /cas delay time t rcd 6 32 9 40 ns 1 /ras to column address delay time t rad 4 20 7 25 ns 1 /cas to /ras precharge time t crp 10 C 10 C ns 2 row address setup time t asr 5C5Cns row address hold time t rah 2C5Cns column address setup time t asc 0C0Cns column address hold time t cah 7C10Cns /oe lead time referenced to /ras t oes 5C5Cns /cas to data setup time t clz 5C5Cns /oe to data setup time t olz 5C5Cns /oe to data delay time t oed 15 C 18 C ns transition time (rise and fall) t t 1 50 1 50 ns refresh time t ref C64C64ms
MC-428LFC72 7 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only ; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. t crp (min.) requirement is applied to /ras, /cas cycles. read cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. access time from /ras t rac C 50 C 60 ns 1 access time from /cas t cac C 18 C 20 ns 1 access time from column address t aa C 30 C 35 ns 1 access time from /oe t oea C 18 C 20 ns column address lead time referenced to /ras t ral 30 C 35 C ns read command setup time t rcs 0C0Cns read command hold time referenced to /ras t rrh C5 C C5 C ns 2 read command hold time referenced to /cas t rch 0C0Cns2 output buffer turn-off delay time from /oe t oez 5 15 5 18 ns 3 /cas hold time to /oe t cho 5C5Cns4 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from /ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. either t rch (min.) or t rrh (min.) should be met in read cycles. 3. t oez(max.) defines the time when the output achieves the condition of hi-z and is not referenced to v oh or v ol . 4. /we: inactive (in read cycle) /cas: inactive, /oe: active t cho is effective. /cas, /oe: active t och is effective.
MC-428LFC72 8 write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. /we hold time referenced to /cas t wch 7C10Cns1 /we pulse width t wp 7C10Cns1 /we lead time referenced to /ras t rwl 18 C 20 C ns /we lead time referenced to /cas t cwl 7C10Cns /we setup time t wcs 0C0Cns2 /oe hold time t oeh 0C0Cns data-in setup time t ds C5 C C5 C ns 3 data-in hold time t dh 12 C 15 C ns 3 notes 1. t wp (min.) is applied to late write cycles or read modify write cycles. in early write cycles, t wch (min.) should be met. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. 3. t ds (min.) and t dh (min.) are referenced to the /cas falling edge in early write cycles. in late write cycles and read modify write cycles, they are referenced to the /we falling edge. read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. read modify write cycle time t rwc 107 C 133 C ns /ras to /we delay time t rwd 59 C 72 C ns 1 /cas to /we delay time t cwd 27 C 32 C ns 1 column address to /we delay time t awd 39 C 47 C ns 1 note 1. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate.
MC-428LFC72 9 hyper page mode (edo) parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t hpc 20 C 25 C ns 1 /ras pulse width t rasp 50 125,000 60 125,000 ns /cas pulse width t hcas 8 10,000 10 10,000 ns /cas precharge time t cp 7C10Cns access time from /cas precharge t acp C 35 C 40 ns /cas precharge to /we delay time t cpwd 41 C 52 C ns 2 /ras hold time from /cas precharge t rhcp 35 C 40 C ns read modify write cycle time t hprwc 52 C 66 C ns data output hold time t dhc 10 C 10 C ns /oe to /cas hold time t och 5C5Cns3 /oe precharge time t oep 5C5Cns output buffer turn-off delay from /we t wez 5 15 5 18 ns 4, 5 /we pulse width t wpz 7C10Cns5 output buffer turn-off delay from /ras t ofr 0 10 0 13 ns 4, 5 output buffer turn-off delay from /cas t ofc 5 15 5 18 ns 4, 5 notes 1. t hpc (min.) is applied to /cas access. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. 3. /we: inactive (in read cycle) /cas: inactive, /oe: active t cho is effective. /cas, /oe: active t och is effective. 4. t ofc (max.) , t ofr (max.) and t wez (max.) define the time when the output achieves the conditions of hi-z and is not referenced to v oh or v ol . 5. to make i/os to hi-z in read cycle, it is necessary to control /ras, /cas, /we, /oe as follows. the effective specification depends on state of each signal. (1) both /ras and /cas are inactive (at the end of the read cycle) /we: inactive, /oe: active t ofc is effective when /ras is inactivated before /cas is inactivated. t ofr is effective when /cas is inactivated before /ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both /ras and /cas are active or either /ras or /cas is active (in read cycle) /we, /oe: inactive t oez is effective. both /ras and /cas are inactive or /ras is active and /cas is inactive (at the end of read cycle) /we, /oe: active and either t rrh or t rch must be met t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective.
MC-428LFC72 10 refresh cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. /cas setup time t csr 10 C 10 C ns /cas hold time (/cas before /ras refresh) t chr 5C5Cns /ras precharge /cas hold time t rpc 0C0Cns /we setup time t wsr 15 C 15 C ns /we hold time t whr 10 C 10 C ns
MC-428LFC72 11 read cycle t rc t ras t rp v ih v il /ras t ofr hi - z t csh data out v ih v il /cas v ih v il address v ih v il /we v ih v il /oe v oh v ol i/o hi - z t ofc t oez t clz t olz t cac t aa t rac t oea t wez t wpz t rrh t rcs row col. t cah t asc t rah t asr t rad t crp t rcd t rsh t cas t cpn t ral t rch t cho t oes t och
MC-428LFC72 12 early write cycle /ras t ras t rc t rp t csh t rsh t rcd t cas t cpn t crp t rad t asr t rah t asc t cah row col. t wcs v ih v il /cas v ih v il address v ih v il /we v ih v il data in i/o v ih v il t ds t wch t dh remark /oe: dont care
MC-428LFC72 13 late write cycle i/o /ras v ih v il /we v ih v il t ras t rp t rc /cas v ih v il t csh t rcd t crp t rsh t cas t cpn address v ih v il t asr t rah t asc t cah t rad row col. t rcs /oe v ih v il v ih v il t cwl t oed data in hi-z t rwl t wp t oeh t ds t dh
MC-428LFC72 14 read modify write cycle i/o /ras v ih v il /we v ih v il t ras t rp t rwc /cas v ih v il t csh t rcd t crp t rsh t cas t cpn address v ih v il t asr t rah t asc t cah t rad row col. t rcs /oe v ih v il v ih v il t rwd t cac data in t awd t cwd t ds t dh t wp t rwl t cwl t aa t rac t oed t oea t oeh i/o v oh v ol data out hi-z hi-z t oez t clz t olz
MC-428LFC72 15 hyper page mode (edo) read cycle /ras /cas address /we /oe i/o t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t rrh t wpz t wez t oez t acp t aa t cac t acp t aa t cac t dhc t dhc t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ofr t ofc t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 16 hyper page mode (edo) read cycle (/we control) /ras /cas address /we /oe v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rasp t rp t crp t rcd t hcas t csh t rhcp t rsh t hcas t cpn t hcas t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rrh t wpz t ofr t ofc t oez t aa t aa t clz t cac t cac t clz t wez t wez t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z i/o t rch t wpz t rcs t rch t wpz t rcs t rch hi - z hi - z t wez t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 17 hyper page mode (edo) read cycle (/oe control) t rasp t rhcp t rp t csh t hpc t rsh t ral t rad t asr t rah t asc t cah t asc t cah t asc t cah t rcs t rch t rrh t oea t oez t aa hi - z hi - z row col.a col.b col.c t oea t acp t oes t olz t crp t rcd t hcas t cp t hcas t cp t hcas t cpn /ras /cas address /oe i/o data out a data out b data out b data out c t ofc t oez t ofr t oea t acp t och t olz t aa t cac t oez t oez t oep t oep t oep t och t och t cho t cho t cho /we t rac t aa t cac t clz t cac t clz v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t olz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 18 hyper page mode (edo) early write cycle /ras t rasp v ih v il /cas v ih v il address v ih v il /we v ih v il i/o v ih v il t rp t rhcp t rsh t hpc t cpn t csh t hcas t cp t hcas t hcas t cp t ral t cah t cah t asc t cah col. col. row t asr t rah t wcs t wcs t rcd t rad t asc col. t wch t wch t wch data in data in data in t dh t ds t dh t ds t dh t ds t wcs t asc t crp remarks 1. /oe: dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 19 hyper page mode (edo) late write cycle /cas v ih v il t cpn t cp t cp t csh t hcas t rcd /ras v ih v il t rasp t rp t crp t hpc t rsh t rhcp t hcas t hcas row col. t asr t rah t rad t asc t cah t asc col. t cah t asc col. t cah t ral address v ih v il /we v ih v il t rcs t cwl t wp t rcs t cwl t wp t rcs t cwl t wp t rwl /oe v ih v il t oeh t oeh t oeh i/o v ih v il t oed t ds t dh hi-z data in t oed t ds t dh data in hi-z t oed t ds t dh data in hi-z remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 20 hyper page mode (edo) read modify write cycle remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle. t rcs /cas v ih v il t cpn t cp t hcas t hcas t cp t hprwc t hcas t rcd /ras v ih v il t rasp t rp t crp address v ih v il t asr t rah t rad t asc t cah t asc t cah t cah t asc row col. col. col. t ral /we v ih v il t rwd t olz i/o v ih v il t dh t ds t awd t cwd t wp t rcs t cwl t acp t cpwd t awd t cwd t wp t cwl t acp t cpwd t awd t cwd t rcs t cwl t rwl t wp /oe v ih v il i/o v oh v ol out t oez t clz t oed t oea t cac t aa t rac in t oea t oeh t cac t aa t olz t dh t ds out t oez t clz t oed in t olz t dh t ds out t oez t clz t oed in t oeh t aa t cac t oea t oeh hi-z hi-z hi-z hi-z
MC-428LFC72 21 hyper page mode (edo) read and write cycle v ih v il /ras v ih v il /cas v ih v il address v ih v il /we v ih v il /oe v oh v ol i/o t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t acp t aa t cac t wez t dhc t oea t rac t aa t cac t clz row col. col. col. data out data out hi - z t oez t wcs t wch hi - z t dh t ds data in i/o v ih v il t cho t olz t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive /cas cycles within the same /ras cycle.
MC-428LFC72 22 /cas before /ras refresh cycle /ras t rc v ih v il /cas v ih v il v ih v il t whr t csr t chr t rpc t csr t chr t rpc t cpn t crp t ras t rp t rp t ras t wsr /we t rc t wsr t whr remark address, /oe: dont care i/o: hi-z /ras only refresh cycle /ras t rc v ih v il /cas v ih v il t asr t crp t rpc t cpn t crp t ras t rp t rp t ras t asr t rc row address v ih v il t rah t rah row remark /we, /oe: dont care i/o: hi-z
MC-428LFC72 23 hidden refresh cycle (read) t rc t rc t ras t rp t rad t ral t asr t rah row col. data out hi - z hi - z t asc t rcs t whr t oes t oea t rac t aa t cac t olz t clz t ofc t oez t cah t rp t ras t crp t rcd t rsh t cpn t chr /ras v ih v il /cas v ih v il /we v ih v il /oe v ih v il i/o v oh v ol address v ih v il t wez t cho t ofr t wpz t rch
MC-428LFC72 24 hidden refresh cycle (write) /ras t ras t rc t ras t chr t rcd t cpn t crp t rad t asc t cah row col. v ih v il /cas v ih v il address v ih v il /we v ih v il i/o t rp t rc t rp t rsh t asr t rah t ds t dh t wcs t wch data in v ih v il t wsr t whr remark /oe: dont care
MC-428LFC72 25 package drawings [MC-428LFC72fh] 168 pin dual in-line module (socket type) item millimeters inches b c 36.83 11.43 0.450 1.450 d d1 2.0 6.35 0.250 0.079 a 133.35 5.250 d2 3.125 0.123 m168s-50a16 w 1.0?.05 0.039 +0.003 ?.002 x 2.54?.10 0.100?.004 y z 3.0 min. 3.0 min. 0.118 min. 0.118 min. e g 6.35 54.61 2.150 0.250 h i 1.27 (t.p.) 0.050 (t.p.) j 23.495 0.925 k 43.18 1.700 l m 31.75?.13 17.78 0.700 1.250?.006 n 4.0 max. 0.158 max. p q r2.0 1.0 0.039 r0.079 r 4.00?.10 0.157 +0.005 ?.004 s t 1.27?.1 0.050?.004 u v 0.25 max. 4.00 min. 0.157 min. 0.010 max. 3.0 f 0.118 f (optional holes) z q n t u y r j a h g i detail of a part detail of b part d2 p d1 w v x s b a1 133.35?.13 5.250?.006 8.89 0.350 m1 m2 19.78 11.97 0.471 0.779 m l e b k c d m2(area a) m1(area b) a(area b) a1(area a)
MC-428LFC72 26 168 pin dual in-line module (socket type) item millimeters inches b c 36.83 11.43 0.450 1.450 d d1 2.0 6.35 0.250 0.079 a 133.35 5.250 d2 3.125 0.123 m168s-50a17-2 w 1.0?.05 0.039 +0.003 ?.002 x 2.54?.10 0.100?.004 y z 3.0 min. 3.0 min. 0.118 min. 0.118 min. e g 6.35 54.61 2.150 0.250 h i 1.27 (t.p.) 0.050 (t.p.) j 23.495 0.925 k 43.18 1.700 l m 31.75?.13 17.78 0.700 1.250?.006 n 9.0 max. 0.355 max. p q r2.0 1.0 0.039 r0.079 r 4.00?.10 0.157 +0.005 ?.004 s t 1.27?.1 0.050?.004 u v 0.25 max. 4.00 min. 0.157 min. 0.010 max. 3.0 f 0.118 f (optional holes) z q t u y r s a b h d g detail of a part detail of b part d2 p d1 w v x i j a1 133.35?.13 5.250?.006 8.89 0.350 m1 m2 19.78 11.97 0.471 0.779 n m l c b k e m2(area b) m1(area a) a1(area b) a(area a) [MC-428LFC72fb]
MC-428LFC72 27 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
MC-428LFC72 2 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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